Rescuing Moore’s Law via Room-Temperature Soliton Integration in Standard Silicon.

Achieving Attosecond-Precision in Direct Digital Synthesis for Phase-Locked Waveform Control.

O(log k) Parallel FHE Conversion IP package featuring pipelined SystemVerilog RTL and Header-Only C++ Library. Designed to accelerate cryptographic pipelines by removing the sequential RNS bottleneck.

A Computational Approach to Sustainable Nitrogen Fixation.