lowRISC / opentitan
OpenTitan: Open source silicon root of trust
See what the GitHub community is most excited about today.
OpenTitan: Open source silicon root of trust
HW Design Collateral for Caliptra RoT IP
Verilator open-source SystemVerilog simulator and lint system
[UNRELEASED] FP div/sqrt unit for transprecision
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
VeeR EL2 Core
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
RISC-V Debug Support for our PULP RISC-V Cores
Common SystemVerilog components
A minimal GPU design in Verilog to learn how GPUs work from the ground up