Build Customized FPGA Implementations for Vivado

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

RISC-V SoC designed by students in UCAS

Example digital project for the Efabless Caravel "openframe" harness

A simple perf model for NPU.

Python iterface for Cadence LEF/DEF parser.

An open-source implementation of the VADL processor description language.

🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

A tool for flow management with a focus on simplicity and fine-grained checkpointing

An unofficial Google Nearby Share/Quick Share app for macOS

GNU toolchain for RISC-V, including GCC

⚠️ DEPRECATED — DEAD for now as YTPlus is now paid.

Chisel: A Modern Hardware Design Language

A submodule of Chipyard https://github.com/ucb-bar/chipyard

Simple RISC-V 3-stage Pipeline in Chisel

chisel tutorial exercises and answers

Generator Bootcamp Material: Learn Chisel the Right Way

A template project for beginning new Chisel work

An RTL-level, Chipyard-compatible DRAM simulator model for high fidelity memory simulations.

🌒 Neovim plugin management inspired by Cargo, powered by luarocks

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

Barduino - A RISC-V based micro-controller inspired by the SiFive FE310 in Sky130 CMOS Process. Built on 151Tapeout Chipyard.

Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development