Must-have verilog systemverilog modules

Various HDL (Verilog) IP Cores

A simple, basic, formally verified UART controller

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

RISC-V microcontroller for embedded, FPGA and ASIC applications

A simple implementation of a UART modem in Verilog.

Simple 8-bit UART realization on Verilog HDL.

UART -> AXI Bridge

Basic Peripheral SoC (SPI, GPIO, Timer, UART)

USB serial device (CDC-ACM)

⚙Hardware Synthesis Laboratory Using Verilog

Basic UART TX/RX module for FPGA

A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植

PID controller on an FPGA with custom RS232 addressing protocol.

👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

verilog modules

Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.